1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to configurations and methods implemented with alternating doped nano-tubes for manufacturing flexibly scalable charge balanced semiconductor power devices with simple manufacturing processes with improved breakdown voltage and significantly reduced resistance.
2. Description of the Prior Art
Semiconductor devices including metal oxide semiconductor field effect transistor (MOSFET) devices configured with vertical super junction structure and electrical characteristics are known and have been disclosed in many patented disclosures. The patented disclosures include U.S. Pat. Nos. 5,438,215, 5,216,275, 4,754,310, 6,828,631. Fujihira further discloses configurations of the vertical super junction devices in the publication “Theory of Semiconductor Super Junction Devices” (Japan Journal of Applied Physics Vol. 36, October 1979 PP 238-241). Specifically, FIG. 1C shows a vertical trench MOSFET super junction device published by Fujihira (FIG. 2A in Fujihira's paper). Fujihira also disclosed in U.S. Pat. No. 6,097,063 a vertical semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively. In U.S. Pat. No. 6,608,350 discloses a vertical super junction device implemented with layers of a dielectric material to fill in the trenches. However, as further discussed below, the configurations and operational characteristics of these super junction devices as disclosed still encounter technical limitations thus restricting the practical usefulness of these devices.
Specifically, conventional manufacturing technologies and device configuration to further increase the breakdown voltage with reduced series resistance, including the devices implemented with super junction structures, are still confronted with manufacturability difficulties. The practical applications and usefulness of the high voltage semiconductor power devices are limited due to the facts that the conventional high power devices generally have structural features that require numerous time-consuming, complex, and expensive manufacturing processes. More particularly, some of the processes for manufacturing the high voltage power devices are complicated thus having low throughput and low yields.
In comparison to conventional technologies, the super-junction technologies have advantages to achieve higher breakdown voltage (BV) without unduly increasing the drain-to-source resistance, Rdson. For standard power transistor cells, breakdown voltage is supported largely on the low-doped drift layer. Therefore, the drift layer is made with greater thickness and with relatively low doping concentration to achieve higher voltage ratings. However this also has the effect of greatly increasing the Rdson resistance. In the conventional power devices, the resistance Rdson has approximately a functional relationship represented by:                Rdson á BV2.5         
In contrast, a device having a super-junction configuration is implemented with a charge balanced drift region. The resistance Rdson has a more favorable functional relationship with the breakdown voltage. The functional relationship can be represented as:                Rdson á BV        
For high voltage applications, it is therefore desirable to improve the device performance by designing and manufacturing the semiconductor power devices with super-junction configurations for reducing the resistance Rdson while achieving high breakdown voltage. Regions adjacent to the channel within the drift region are formed with an opposite conductivity type. The drift region may be relatively highly doped, so long as the regions adjacent to the channel are similarly doped but of an opposite conductivity type. During the off state, the charges of the two regions balance out such that the drift region becomes depleted, and can support a high voltage. This is referred to as the super junction effect. During the on state, the drift region has a lower resistance Rdson because of a higher doping concentration. Studies have shown that a dopant concentration of 1E12/cm2 is optimal for the drift region of a super junction device.
However, conventional super-junction technologies still have technical limitations and difficulties when implemented to manufacture the power devices. Furthermore, the manufacturing processes often require equipment not compatible with standard foundry processes. Additionally, these devices have structural features and manufacturing processes not conducive to scalability for low to high voltage applications. In other words, some approaches would become too costly and/or too lengthy to be applied to higher voltage ratings. Also in the prior art devices, it is difficult to manufacture thin vertical channels for the superjunction regions. As will be further reviewed and discussions below, these conventional devices with different structural features and manufactured by various processing methods, each has limitations and difficulties that hinder practical applications of these devices as now demanded in the marketplace.
There are three basic types of semiconductor power device structures for high voltage applications. The first type includes those device formed with standard structures as depicted in FIG. 1A for a standard VDMOS that do not incorporate the functional feature of charge balance. For this reason, there is no breakdown voltage enhancement beyond the one-dimensional theoretical figure of merit, i.e., the Johnson limit, according to the I-V performance measurements and further confirmed by simulation analyses of this type of devices. The devices with this structure generally have relatively high on-resistance due to the low drain drift region doping concentration in order to satisfy the high breakdown voltage requirement. In order to reduce the on resistance Rdson, this type of devices generally requires large die size. Despite the advantages that the devices can be manufactured with simple processes and low manufacturing cost, these devices are however not feasible for high current low resistance applications in the standard packages due the above discussed drawbacks: the die cost becomes prohibitive (because there are too few dies per wafer) and it becomes impossible to fit the larger die in the standard accepted packages.
The second type of devices includes structures provided with two-dimensional charge balance to achieve a breakdown voltage higher than the Johnson limit for a given resistance, or a lower specific resistance (Rdson*Area product) than the Johnson limit for a given breakdown voltage. This type of device structure is generally referred to as devices implemented with the super junction technology. In the super junction structure, a charge-balance along a direction parallel to the current flow in the drift drain region of a vertical device, based on PN junctions or by field plate techniques as that implemented in oxide bypassed devices to enable a device to achieve a higher breakdown voltage. The third type of structure involves a three-dimensional charge-balance where the coupling is both in the lateral as well as the vertical directions. Since the purpose of this invention is to improve the structural configurations and manufacturing processes of devices implemented with super junction technologies to achieve two-dimensional charge balance, the limitations and difficulties of devices with super junction will be reviewed and discussed below.
FIG. 1B is a cross sectional view of a device with super junction to reduce the specific resistance (Rsp, resistance times active area) of the device by increasing the drain dopant concentration in the drift region while maintaining the specified breakdown voltage. The charge balance is achieved by providing P-type vertical columns formed in the drain to result in lateral and complete depletion of the drain at high voltage to thus pinch off and shield the channel from the high voltage drain at the N+ substrate. Such technologies have been disclosed in Europe Patent 0053854 (1982), U.S. Pat. No. 4,754,310, specifically in FIG. 13 of that Patent and U.S. Pat. No. 5,216,275. In these previous disclosures, the vertical super junctions are formed as vertical columns of N and P type dopant. In vertical DMOS devices, the vertical charge balance is achieved by a structure with sidewall doping to form one of the doped columns as were illustrated in drawings. In addition to doped columns, doped floating islands have been implemented to increase the breakdown voltage or to reduce the resistance as disclosed by U.S. Pat. No. 4,134,123 and U.S. Pat. No. 6,037,632. Such device structure of super junction still relies on the depletion of the P-regions to shield the gate/channel from the drain. The floating island structure is limited by the technical difficulties due to charge storage and switching issues. It is difficult to form vertical columns of alternating conductivity types, particularly when the columns are deep and/or when the widths of the columns are small. For super junction types of devices, the manufacturing methods are generally very complex, expensive and require long processing time due to the facts that the methods require multiple steps and several of these steps are slow and have a low throughput.
Additionally, for vertical super-junction devices (VSJD), the manufacturing processes either have difficulties in etching or filling the trenches. Major problems include the requirement to filling the trenches with epitaxial (epi) layers without void at the interface of the epitaxial layers covering the sidewalls are merged at the center of the trench. FIG. 1D (FIG. 1 of U.S. Pat. No. 6,608,350) shows the gap filling difficulties when the sidewalls are substantially 90 degrees with voids formed when filling up the gaps (FIG. 1D). Furthermore, the charge balance and the breakdown voltage are very sensitive to the sidewall angles of the trenches. Furthermore, the device performance is degraded with the wider P and N columns due to multiple epitaxial and boron implants according to the processes of the conventional methods. These manufacturing processes also increase the production costs. For these reasons, the conventional structures and manufacture methods are limited by slow and expensive manufacturing processes and are not economical for broad applications.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices such that the above discussed problems and limitations can be resolved.